Title  Partner(s) Author(s) Link
HW/SW-database-codesign for compressed bitmap index processing TU Dresden Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis, Wolfgang Lehner

10.1109/ASAP.2016.7760772
Body biasing for analog design: Practical experiences in 22 nm FD-SOI Fraunhofer Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich 10.1109/DDECS.2017.7934580
MESH: Explicit and Flexible Generation of Analog Arrays Fraunhofer  Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig  
Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier IDT Hua Lv, Diana C. Leitao, Zhiwei Hou, Paulo P. Freitas, Susana Cardoso, Thomas Kämpfe, Johannes Müller, Juergen Langer, Jerzy Wrona 10.1063/1.5007656
Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator TU Dresden Yong Chen, Emil Matus, Gerhard P. Fettweis 10.1109/ISVLSI.2017.27
Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism TU Dresden Yong Chen, Emil Matus, Gerhard P. Fettweis 10.1109/ISCAS.2017.8050829
Dynamic voltage and frequency scaling for neuromorphic many-core systems TU Dresden Sebastian Hoppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumarker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis Plana, Jim Garside, Simon Davison, David R. Lester, Steve Furber 10.1109/ISCAS.2017.8050656
A fixed point exponential function accelerator for a neuromorphic many-core system TU Dresden Johannes Partzsch, Sebastian Hoppner, Matthias Eberlein, Rene Schuffny, Christian Mayr, David R. Lester, Steve Furber 10.1109/ISCAS.2017.8050528
Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD Soitec W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B.-Y. Nguyen 10.1109/S3S.2016.7804377 
       
       
       
       
Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

Soitec

Schwarzenbach, W.; Allibert, F.; Le Royer, C.; Grenouillet, L.; Malaquin, C.; Bertrand-Giuliani, C.; Boedt, F.; Loubriat, S.; Michau, C.; Parissi, D.; Nguyen, B.-Y. 10.1109/s3s.2016.7804377
Body biasing for analog design: Practical experiences in 22 nm FD-SOI Fraunhofer Rao, Sunil Satish; Prautsch, Benjamin; Shrivastava, Ashish; Reich, Torsten 10.1109/ddecs.2017.7934580
Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism TU Dresden Chen, Yong; Matus, Emil; Fettweis, Gerhard P. 10.1109/iscas.2017.8050829
Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator TU Dresden Chen, Yong; Matus, Emil; Fettweis, Gerhard P. 10.1109/isvlsi.2017.27
HW/SW-database-codesign for compressed bitmap index processing TU Dresden Haas, Sebastian; Karnagel, Tomas; Arnold, Olive 10.1109/asap.2016.7760772
A fixed point exponential function accelerator for a neuromorphic many-core s TU Dresden Partzsch, Johannes; Hoppner, Sebastian; Eberlein, Matthias; Schuffny, Rene; Mayr, Christian; Lester, David R.; Furber, Steve 10.1109/iscas.2017.8050528
Dynamic voltage and frequency scaling for neuromorphic many-core systems TU Dresden Hoppner, Sebastian; Yan, Yexin; Vogginger, Bernhard; Dixius, Andreas; Partzsch, Johannes; Neumarker, Felix; Hartmann, Stephan; Schiefer, Stefan; Scholze, Stefan; Ellguth, Georg; Cederstroem, Love; Eberlein, Matthias; Mayr, Christian; Temple, Steve; Plana, Luis; Garside, Jim; Davison, Simon; Lester, David R.; Furber, Steve 10.1109/iscas.2017.8050656