The goal of the PRIME project is to establish an open ultra-low power technology platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution.

These types of applications operated with batteries or energy scavenging will require ultra-low power systems optimized for very low cost. The European Industry has already a solid background, knowledge and track record to provide low power System On Chip to the global market. Long term strategy of the chip makers such as ST Microelectronics and Global Foundries (GF Dresden) is to target the market of mobile devices backed up the development of Fully Depleted Silicon On Insulator (SOI) Technology which today is commercially available in 28nm technology node.
The future IoT systems and devices will have to be optimized for low cost and considerably reduced operating and standby power compared to what is currently state-of-the-art. The new emerging non-volatile memories such as STT RAM or Resistive RAM appear to be promising alternatives to the conventional embedded Flash or e-DRAM memories due to their competitive integration costs, lower programming power and improved performance.

The PRIME project will aim at the exploration and the validation of innovative low power Logic and embedded Memories technologies by building and demonstrating capability of the main sub-blocks components of the IoT architecture.

There are 5 technical work packages in this project:

WP2: System Study for Ultra Low Power platforms:

The objective of this workpackage is to explore the technology and memory requirements in the IoT systems driven by the applications use cases in the medical, agricultural, domestics and security domains. Within the project two types of IoT nodes are considered: High Performance and Ultra Low Power devices.

Based on the input of partners from the application side, the requirements of both types in terms of memory specification and compute performance are defined. This requirement specification will also cover other aspects such as varying power modes and expected duty cycling.

Based on these two senarios, the trade-off between different memory solutions is quantified revealing their specific benefits. The quantitative analysis is used to define target performance levels in terms of speed, power, size and retention time. This will also cover the performance goals for the digital domain as well as efficiency targets of the power delivery.

WP3: Ultra-Low Power Technologies: Logic, e-NVM:

This work package will develop the technological platform required for the design activities and system applications targeted in WP 2, 4 and 5. This includes the development and reliability testing of a highly disruptive low power technology platform based on a fully depleted silicon on insulator technology and the development and testing of advanced low power memory technologies based on magnetic (perpendicular STT-MRAM) or filamentary (oxide based RRAM) resistive switching phenomena. This defines the main objectives of WP3 as follows:

  • Development of a 22nm fully depleted low power CMOS technology platform with back-biased transistor options for active power management and analog (capacitors, inductors, resistors) and basic RF 3 elements of predevelopment are integrated into a manufacturable technology a) device (from ST Microelectronics 14nm ) b) the superior gate stack (from GF 28nm technology in Dresden) c) parts from BEOL (from 14nm GF-technology in Malta). Physical gate length is shrunk to 24nm. With these devices performance abilities of 14nm FinFET are targeted.
  • Assessment of a perpendicular STT-MRAM cell concept as a non-volatile embedded memory solution for a 28 nm CMOS Next to the identification of a suitable material stack with perpendicular magnetization the manufacturability of this new memory technology as a foundry solution needs to be evaluated in terms of suitable access transistor performance and reliability, BEOL integration flow and cross contamination risks.
  • Single cell design and development of BEOL test array implementation of RRAM memory with special focus on the trade-off between device scaling, performance and Benchmarking of different RRAM cell concepts on a 28 nm SLP bulk technology as well as on a 28 nm FDSOI technology is targeted.

These objectives are motivated by the paradigm shift from high performance to ultra-low power and the mobile application trend currently observed in microelectronics. In this context the new 22nm FDSOI technology can provide the following advantages compared to bulk technologies:

  • Improved sub VT-behaviour ,
  • lower Drain Induced Barrier Lowering (DIBL),
  • excellent electrostatic control,
  • improved output-characteristics,
  • lower junction leakage

Especially for the SRAM-devices a lower variability is determining the manufacturability of the SoCs. The FDSOI- device-concept enables lower variability by

  • superior VT-L roll-off,
  • no doping in the channel regions, therefore practically no random dopant fluctuation,
  • only single spacer required,
  • SOI-concepts limit depths of junctions (no scattering in this direction).

Several device-suites for 22nm FDSOI will be developed, with different operating points of the digital transistors leading to 3 technology flavors 1) ULL (Ultra Low Leakage) for highest energy efficiency, 2) RVT/HVT (Regular Voltage Transistor/ High Voltage Transistor) high energy efficiency combined with high performance (with Reverse Back Bias option) and 3) SLVT / LVT (Super-low VT / Low VT) for highest performance (with Forward Back Bias option).

In order to be attractive for different customers addressing ultra-low power designs for varies applications, base CMOS processes in any foundry need to be enhanced by additional offerings. One of these typical offerings being used in consumer, industrial and automotive products is a non-volatile memory (NVM). In contrast to the typical base CMOS SRAM memory arrays, these NVMs can store their data even without power supplied to the chip. Traditional cell concepts being used to create embedded non-volatile memories have been different types of flash memory cells (e.g. split gate cells), which usually require high voltages to operate (appr. 10 V) and which cause a significant disruption to the base FEOL process. Additional 10-15 masks required for co-integration of embedded NVM increase dramatically the cost of a final product. In addition, these types of cells do not scale very well with advanced technology nodes.

For these reasons, more advanced non-volatile memory concepts have been developed and investigated in the past years. The most promising among these cell concepts are the STT-MRAM cell and the metal oxide based RRAM cells. The STT-MRAM cell utilizes a magnetic tunnel junction (MTJ), which depending on the spin orientation can provide two resistance states. It typically consists of one fixed magnetic layer, one barrier layer and one free magnetic layer. The free layer can be switched from one magnetic polarization to the opposite and hence allows electrons to pass the junction or not. GLOBALFOUNDRIES focuses on e-Flash market applications like smart card or automotive with the following specifications:

  • highest core frequencies, g. 100 MHz and 500 MHz,
  • largest ranges of operation junction temperatures, g. -40 °C-110°C and --40 °C-175°C,
  • Access times of 20 ns or 50 ns,
  • Endurance cycles 105 and
  • Retention 10 y, for some applications 20

A similar resistance change can be observed in RRAM cells. However, the underlying physical mechanism is markedly different compared to that of MRAM. In the case of oxide based RRAM a valence change effect in transition metal oxide (TMO) based metal-insulator-metal structures is used to code the memory state. After forming, a conducting filament formed by clustered oxygen vacancies is extending through a high-resistance dielectric between two electrodes. This filament can be partly dissolved or enhanced by a voltage/electric field controlled redistribution of oxygen vacancies, which yields high and low resistance memory states. The ease of manufacturing of such structures and their superior scalability make them very attractive as embedded NVM. In contrast to the MRAM cells, the RRAM is based on well- established oxides (i.e. HfO2 or TaO2), in which these small conductive filaments can easily be formed.

In addition to the resistive switching elements (MTJ or RRAM stack), which can be integrated in the BEOL above Logic devices, the memory cell requires one access transistor in the FEOL. The selection device has to be integrated into the 28nm POR while maintaining the full functionality performance and reliability of the complete device suite including the selection device. Therefore, a new POR will be generated with relaxed thermal budget due to the inclusion of the MRAM stack and encapsulation. With the favourized BEOL-configuration, integration of new memories requires only 3 additional masks which reduces the processing costs dramatically as compared to the standard e-NVM NOR Flash process flow.

In contrast to traditional flash cells, STT-MRAM (perpendicular magnetization) and oxide based RRAM memory elements are considered to scale well down to at least 20 nm, maybe even 10 nm technology nodes. However, the total size of the cell (1T1R) will likely depend on the size of the select device determined by the current and voltages needed for programming. The major size advantage with respect to the conventional embedded flash memory will come from the scaled periphery area due to reduced or eliminated charge pumps needed for memory array to satisfy high programming voltage. It is expected that new memories will not disrupt the other FEOL devices, as the storage element is integrated into the BEOL, typically in a high metal level using low temperature processes.

In summary, the RRAM offers the lowest manufacturing complexity. Typical access times are slightly higher compared to the STT-MRAM cell, and cycling endurance is typically limited to 106 cycles, which is lower than the superior numbers which are reported for STT-MRAM. Hence, RRAM might be the 1st choice for low-cost IoT applications, while STT-MRAM supports the applications, which require higher memory performance at slightly higher costs. Both memory types together are the optimal combination to facilitate the large variety of memory requirements of a highly performant but low-power FD-SOI technology. A multi-purpose test-chip will allow the efficient implementation of both memory cell types with the goal of cell optimization based on statistical analyses.

WP4: Design ecosystem for Ultra Low Power technology platforms:

Objective of this work package is to develop the key components to enable a flexible design ecosystem for ultra-low- power technology platforms enabling IoT products. This includes IP as well as design flow development.

Targeting the specific needs of an IoT node requiring extremely low power combined with low duty cycling, new and innovative modules to support this use case in the digital domain will be developed. This will include:

  • Memory block design and compiler development using novel sense techniques and associated sense amplifier designs
  • Memory management units controlling the access and assignment to addressing space allowing a flexible
  • Innovative architectures for ultra-low-power application specific processing elements
  • Security building blocks for IoT devices based on PUF PUFs are Physically Unclonable Functions and can be considered to be “device fingerprints” of ICs that can be used for authentication as well as for generating and securely storing cryptographic keys
  • Novel power management unit architectures to optimize the power budget on the system

IoT applications inherently rely on sensing and/or acting with the “real” analogue world. Thus, a set of basic analogue building blocks and analogue/digital converters is necessary to enable the design of corresponding analogue frontends. To benefit from FDSOI features such as back gate biasing and thus avoiding system performance drops caused by analogue parts, novel architectures of fundamental analogue and mixed-signal IP such as converters are necessary and will be investigated.

Moreover, the development of a technology-independent design flow for the design ecosystem will enable circuit and system design entities to have quick and affordable access to leading-edge technologies, addressed within PRIME. Especially the demand on first-time-right designs and high IP reuse in the case of technology migration is a critical feature when developing mixed-signal ICs and will be supported by the novel design flow. Such soft IP solutions, combining design data generation for any performance variants, extensible support of various tech nodes and flavours, and full compatibility with most of the common design tools, are not yet available but will boost availability of mixed- signal IPs for the new tech nodes.

WP5: Platform architectures for Ultra Low Power applications:

Objective of this work package is to develop the key components to enable a flexible design ecosystem for ultra-low- power technology platforms enabling IoT products. This includes IP as well as design flow development.

Targeting the specific needs of an IoT node requiring extremely low power combined with low duty cycling, new and innovative modules to support this use case in the digital domain will be developed. This will include:

  • Memory block design and compiler development using novel sense techniques and associated sense amplifier designs
  • Memory management units controlling the access and assignment to addressing space allowing a flexible
  • Innovative architectures for ultra-low-power application specific processing elements
  • Security building blocks for IoT devices based on PUF PUFs are Physically Unclonable Functions and can be considered to be “device fingerprints” of ICs that can be used for authentication as well as for generating and securely storing cryptographic keys
  • Novel power management unit architectures to optimize the power budget on the system

IoT applications inherently rely on sensing and/or acting with the “real” analogue world. Thus, a set of basic analogue building blocks and analogue/digital converters is necessary to enable the design of corresponding analogue frontends. To benefit from FDSOI features such as back gate biasing and thus avoiding system performance drops caused by analogue parts, novel architectures of fundamental analogue and mixed-signal IP such as converters are necessary and will be investigated.

Moreover, the development of a technology-independent design flow for the design ecosystem will enable circuit and system design entities to have quick and affordable access to leading-edge technologies, addressed within PRIME. Especially the demand on first-time-right designs and high IP reuse in the case of technology migration is a critical feature when developing mixed-signal ICs and will be supported by the novel design flow. Such soft IP solutions, combining design data generation for any performance variants, extensible support of various tech nodes and flavours, and full compatibility with most of the common design tools, are not yet available but will boost availability of mixed- signal IPs for the new tech nodes.

WP6: Demonstrators:

Demonstrators will show the proposed low-power, wireless solutions which will be integrated with selected non-volatile memory to demonstrate performance and functionality of the delivered design and technology block.

IMEC-NL will provide a demonstration board, for the Swarm Node SoC. Software is developed to demonstrate the IC in a Swarm use case. Complete evaluation of power consumption and performance of this IC is conducted. This enables an evaluation of the initial assessment of WP2 on requirements and optimizations. Finally feedback for future optimization of eNVM memories and for IoT architectures is provided.

Synopsys will demonstrate the power consumption benefits of the IP developed in WP4 in the application context of 9D sensor fusion, voice and face activation

ST and CEZAMAT will provide design and realization a PCB board enabling the mix of several methodologies of localization, including Angle-of-Arrival with multi-antenna scheme.

Intrinsic-ID will be developing a demonstrator with specific focus on solving security use cases for the IoT market. Intrinsic-ID will create a demonstrator that shows the properties of the designed security architecture for low-power IoT environments. This demonstrator will show how use cases like strong authentication and secure key storage can be dealt with using PUF technology.

Technolution will demonstrate the developed technologies in at least one realistic use case in the domains mentioned in WP1. To this end, Techolution will include the developed devices and boards in a real life use case. The definition of the case will be made during the course of the project to align with the most recent developments in the market. Current cases that could be considered include cooperative driving (cars as sensor nodes), condition based farming in agriculture and asset monitoring.

GF will design a 22FDSOI Test Chip to test functionality of digital devices, passive devices and RF-devices during process development. Special structures are used for characterization of back bias options and energy consumption during operation. Additional structures will be used for performance and reliability testing. The testchip contains all devices in different sizes to control e.g. device Roll-Off, resistances of layers or capacitors. Different structures are used for characterizing edge effects or homogeneity of relevant layers like e.g. Workfunction layers. With this demonstrator basic data can be obtained to extract design parameter for products in various application domains, like Consumer, Wearables, IoT/Industrial, Mainstream Mobile, Auto/Info and WiFi/RF. In addition a Multiple Purpose memory test- chip will be developed based on a 28nm technology, enabling the efficient integration of the different resistive memory cells, which are mandatory to facilitate the large variety of memory requirements of the FD-SOI technology. Based on the test-chip the integration of STT-MRAM cells as well as ReRAM cells into a large cell array will be realized. The test-chip enables the statistical characterization of the memory cells as an important prerequisite for cell optimization. Statistical fluctuation is one of the most relevant characteristics of a memory technology, determining scalability, memory density and reliability. The requirement specs for the multi-purpose test-chip will be gathered from all project partners (IMEC- B, LETI, FhG-IPMS) based on single cell data and the concept for multi-purpose test-chip will be developed (NaMLab). The final demonstrator of TUD shows the manufactured MPSoC. High-throughput IoT applications will run while demonstrating the integrated power control mechanisms.

In the end of the work package, an advanced cost-efficient technology platform optimized for ultra low power solutions will be available and validated by number of demonstrators presenting the most critical system blocks. It can allow attracting potential SMEs interested in the application of the technology platform in market applications.